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ltc3785 3785fc typical a pplica t ion descrip t ion 10v, high effciency, synchronous, no r sense buck-boost controller the ltc ? 3785 is a high power synchronous buck-boost controller that drives all n-channel power mosfets from input voltages above, below and equal to the output volt- age. with an input range of 2.7v to 10v, the ltc3785 is well suited for a wide variety of single or dual cell li-ion or multicell alkaline/nimh applications. the operating frequency can be programmed from 100khz to 1mhz. the soft-start time and current limit are also programmable. the soft-start capacitor doubles as the fault timer which can program the ic to latch off or recycle after a determined off time. burst mode opera- tion is user controlled and can be enabled by driving the mode pin high. protection features include foldback current limit, short- circuit and overvoltage protection. l , lt, ltc, ltm, linear technology, the linear logo and burst mode are registered trademarks of linear technology corporation. no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. effciency vs input voltage fea t ures a pplica t ions n single inductor architecture allows v in above, below or equal to v out n 2.7v to 10v input and output range n up to 96% effciency n up to 10a of output current n all n-channel mosfets, no r sense ? n true output disconnect during shutdown n programmable current limit and soft-start n optional short-circuit shutdown timer n output overvoltage and undervoltage protection n programmable frequency: 100khz to 1mhz n selectable burst mode ? operation n available in 24-lead (4mm 4mm) exposed pad qfn package n palmtop computers n handheld instruments n wireless modems n cellular telephones v cc i svin tg1 v sense bg1 fb v c tg2 bg2 sw2 3785 ta01a v bst1 sw1 i ssw1 i svout rt v drv i ssw2 v bst2 ccm i lset mode run/ss v in v out ltc3785 gnd 4.7f v in 2.7v to 10v v out 3.3v 5a 22f 4.7h 100f 0.22f 0.22f 270pf 1.3k 205k 121k 12k 42.2k 59k 121k 205k 1nf 1nf v in (v) 2.5 efficiency (%) 95 10 3785 ta01b 90 85 4 5.5 7 8.5 100 i load = 1a v out = 3.3v f osc = 500khz i load = 2a
ltc3785 3785fc the l denotes the specifcations which apply over the full operating junction temperature range, otherwise specifcations are at t a = 25c. v in = i svout = v drv = v bst1 = v bst2 = 3.6v, r t = 49.9k, r ilset = 59k. p in c on f igura t ion a bsolu t e maxi m u m r a t ings input supply voltage (v in ) ......................... C0.3v to 11v i svout , i svin .............................................. C0.3v to 11v sw1, sw2, i ssw1 , i ssw2 voltage: dc ............................................................. C1v to 11v pulsed, <1 s ............................................. C2v to 12v run/ss, mode, ccm, v drv , v cc voltages .. C0.3v to 6v v bst1 voltage ............................................. C0.3v to 16v with respect to sw1 ............................... C0.3v to 6v v bst2 voltage ............................................. C0.3v to 16v with respect to sw2 ............................... C0.3v to 6v peak driver output current < 10s (tg1, tg2, bg1, bg2) .................................................3a v cc average output current .................................100ma operating junction temperature range (note 2) .................................................. C40c to 125c junction temperature ........................................... 125c storage temperature range ................... C65c to 150c (note 1) 24 23 22 21 20 19 7 8 9 top view 25 gnd uf package 24-lead (4mm s 4mm) plastic qfn 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 run/ss v c fb v sense i lset ccm i ssw1 bg1 v drv bg2 i ssw2 sw2 v in v cc i svin v bst1 tg1 sw1 rt mode nc i svout v bst2 tg2 t jmax = 125c, q ja = 40c/w 1 layer board, q ja = 30c/w 4 layer board exposed pad (pin 25) is gnd, must be soldered to pcb parameter conditions min typ max units v in supply input operating voltage l 2.7 10 v quiescent currentburst mode operation v c = 0v, mode = 3.6v (note 4) 86 200 a quiescent currentshutdown run/ss = 0v, i svout = 3.6v 15 25 a quiescent currentactive mode = 0v (note 4) 0.8 1.5 ma error amp feedback voltage (note 5) l 1.200 1.225 1.25 v feedback input current 1 500 na o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3785euf#pbf ltc3785euf#trpbf 3785 24-lead (4mm s 4mm) plastic qfn C40c to 85c ltc3785iuf#pbf ltc3785iuf#trpbf 3785 24-lead (4mm s 4mm) plastic qfn C40c to 125c lead based finish tape and reel part marking* package description temperature range ltc3785euf ltc3785euf#tr 3785 24-lead (4mm s 4mm) plastic qfn C40c to 85c ltc3785iuf ltc3785iuf#tr 3785 24-lead (4mm s 4mm) plastic qfn C40c to 125c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ e lec t rical c harac t eris t ics
ltc3785 3785fc the l denotes the specifcations which apply over the full operating junction temperature range, otherwise specifcations are at t a = 25c. v in = i svout = v drv = v bst1 = v bst2 = 3.6v, r t = 49.9k, r ilset = 59k. e lec t rical c harac t eris t ics parameter conditions min typ max units error amp source current C500 a error amp sink current 900 a error amp a vol 90 db overvoltage threshold v sense pin % above fb ltc3785e l tc3785i l l 6 6 10 10 14 15 % % undervoltage threshold v sense pin % below fb ltc3785e l tc3785i l l C3.5 C3.5 C6.5 C6.5 C9.5 C10.5 % % v sense input current v sense = measured fb voltage 1 500 na v cc regulator v cc maximum regulating voltage v in = 5v, i vcc = C20ma l 4.15 4.35 4.55 v v cc regulation voltage v in = 3.6v, i vcc = C20ma l 3.3 3.5 3.6 v v cc regulator sink current i svout = v cc = 5v 800 a run/soft-start run/ss threshold when ic is enabled when ea is at maximum boost duty cycle l 0.35 0.7 1.9 1.1 v v run/ss input current run/ss = 0v C1 a run/ss discharge current during current limit 20 30 a current limit current limit sense threshold i svin to i ssw1 , r ilset = 121k i svin to i ssw1 , r ilset = 59k l l 20 55 60 105 100 155 mv mv reverse current limit sense threshold i ssw2 to i svout , ccm > 2v i ssw2 to i svout , ccm < 0.4v, ltc3785e i ssw2 to i svout , ccm < 0.4v, ltc3785i l l C50 C110 C15 C15 C170 C35 C40 mv mv mv input current i svin i svout i ssw1 , i ssw2 80 10 0.1 150 20 5 a a a ccm input threshold (high) l 2.2 v ccm input threshold (low) l 0.4 v ccm input current ccm = 3.6v 0.01 1 a burst mode operation mode threshold l 0.8 1.5 2.2 v mode input current 0.01 1 a t on time 1.4 s oscillator frequency accuracy l 370 509 650 khz switching characteristics maximum duty cycle boost (% switch bg2 on) buck (% switch tg1 on) l 80 90 99 % % tg1, tg2 driver impedance 2 bg1, bg2 driver impedance 2 tg1, tg2 rise time c load = 3300pf (note 3) 20 ns
ltc3785 3785fc the l denotes the specifcations which apply over the full operating junction temperature range, otherwise specifcations are at t a = 25c. v in = i svout = v drv = v bst1 = v bst2 = 3.6v, r t = 49.9k, r ilset = 59k. elec t rical c harac t eris t ics li-ion to 3.3v effciency vs load current two li-ion to 7v effciency vs load current li-ion/9v to 5v v out effciency vs load current burst mode ripple line transient response v out load transient t a = 25c, unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3785e is guaranteed to meet performance specifcations from 0c to 85c. specifcations over the C40c to 85c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3785i is guaranteed typical p er f or m ance c harac t eris t ics load current (a) 0.0001 efficiency (%) 60 80 100 1 3785 g01 40 20 50 70 90 30 10 0 0.001 0.01 0.1 10 v in = 4.2v v in = 3.6v v in = 3v burst mode operation fixed frequency mosfet si7940 l = 4.7 h wurth we-pd f osc = 500khz load current (a) 0.0001 0.001 0.01 0.1 1 40 efficiency (%) 50 60 70 80 10 3785 g02 30 20 10 0 90 100 v in = 8.4v v in = 7.2v v in = 5.4v mosfet si7940 l = 5.6h mss1260 f osc = 430khz burst mode operation fixed frequency load current (a) 0.0001 0.001 0.01 0.1 1 40 efficiency (%) 50 60 70 80 10 3785 g03 30 20 10 0 90 100 v in = 9v v in = 4.2v v in = 3.6v v in = 2.7v mosfet si7940 l = 5.6h mss1260 f osc = 430khz burst mode operation fixed frequency v out 50mv/div ac coupled inductor current 1a/div 5s/div v out = 3.3v c out = 100f 3785 g04 v out 500mv/ div v in 3v to 8.5v 500s/div i load = 300ma v out = 5v c out = 100f 3785 g05 v out 200mv/ div i load 10ma to 2a 100s/div v in = 3.6v v out = 3.3v c out = 100f 3785 g06 to meet performance specifcations over the full C40c to 125c operating junction temperature range. note 3: specifcation is guaranteed by design and not 100% tested in production. note 4: current measurements are performed when the outputs are not switching. note 5: the ic is tested in a feedback loop to make the measurement. parameter conditions min typ max units bg1, bg2 rise time c load = 3300pf (note 3) 20 ns tg1, tg2 fall time c load = 3300pf (note 3) 20 ns bg1, bg2 fall time c load = 3300pf (note 3) 20 ns buck driver nonoverlap time tg1 to bg1 100 ns boost driver nonoverlap time tg2 to bg2 100 ns
ltc3785 3785fc typical p er f or m ance c harac t eris t ics v in start-up voltage vs temperature v in burst quiescent current vs temperature ov and uv thresholds vs temperature v fb vs temperature normalized oscillator frequency vs temperature oscillator frequency vs rt t a = 25c, unless otherwise noted. p in func t ions run/ss (pin 1): run control and soft-start input. an internal 1a charges the soft-start capacitor and will charge to approximately 2.5v. during a current limit fault, the soft-start capacitor will incrementally discharge. once the pin drops below 1.225v the ic will enter fault mode, turning off the outputs for 32 times the soft-start time. if >5a (at run/ss = 1.225v) is applied externally, the part will latch off after a fault is detected. if >40a (at run/ss = 1.225v) is applied externally, current limit faults will not discharge the ss capacitor. v c (pin 2): error amp output. a frequency compensa- tion network is connected from this pin to the fb pin to compensate the loop. see closing the feedback loop in the applications information section for guidelines. fb (pin 3): feedback pin. connect resistor divider tap here. the feedback reference voltage is typically 1.225v the output voltage can be adjusted from 2.7v to 10v ac- cording to the following formula: v out = 1.225v ? r1 + r2 r2 temperature (c) ?50 1.2255 1.2245 1.2250 1.2240 1.2235 1.2230 1.2225 1.2220 1.2215 25 75 3785 g07 ?25 0 50 150125100 v fb (v) temperature (c) ?50 25 75 ?25 0 50 150125100 ?1.0 change from 25c (%) ?0.6 ?0.2 0.2 3785 g08 0.6 1.0 ?0.8 ?0.4 0 0.4 0.8 rt (k) 20 0 oscillator frequency (khz) 200 400 600 800 1000 1200 40 60 80 100 3785 g09 temperature (c) ?50 25 75 ?25 0 50 150125100 2.465 v in start-up voltage (v) 2.470 2.475 2.480 2.485 2.490 3785 g10 temperature (c) ?50 25 75 ?25 0 50 150125100 v in current (a) 3785 g11 80 85 100 90 95 temperature (c) ?50 25 75 ?25 0 50 150125100 ?8 threshold (%) ?4 0 4 3785 g12 8 12 ?6 ?2 2 6 10 ov threshold uv threshold
ltc3785 3785fc p in func t ions v sense (pin 4): overvoltage and undervoltage sense. the overvoltage threshold is internally set 10% above the regulated fb voltage and the undervoltage threshold is internally set 6.5% below the fb regulated voltage. this pin can be tied to fb but to optimize the response time it is recommended that a voltage divider from v out be ap- plied. the divider can be skewed from the feedback value to achieve the desired uv or ov threshold. i lset (pin 5): current limit set. a resistor from this pin to ground sets the current limit threshold from the i svin and i ssw1 pins. ccm (pin 6): continuous conduction mode control pin. when set low, the inductor current is allowed to go slightly negative (C15mv referenced to the i svout C i ssw2 pins). when driven high, the reverse current limit is set to the similar value of the forward current limit set by the i lset pin. rt (pin 7): oscillator programming pin. a resistor from this pin to gnd sets the free-running frequency of the ic. f r mhz osc t ? ? ? ? ? ? ? 25000 mode (pin 8): burst mode control pin. ? mode = high: enable burst mode operation. in burst mode operation the operation is variable frequency, which provides a signifcant effciency improvement at light loads. the burst mode operation will continue until the pin is driven low. ? m ode = low: disable burst mode operation and maintain low noise, constant frequency operation. nc (pin 9): no connect. there is no electrical connection to this pin inside the package. i svout (pin 10): reverse current limit comparator non- inverting input. this pin is normally connected to the drain of the n-channel mosfet d (tg2 driven). v bst2 (pin 11): boosted floating driver supply for boost switch d. this pin will swing from a diode below v cc up to v out + v cc C v diode . sw2 (pin 13): ground reference for driver d. gate drive from tg2 will reference to the common point of output switches c and d. i ssw2 (pin 14): reverse current limit comparator invert- ing input. this pin is normally connected to the source of the n-channel mosfet d (tg2 driven). v drv (pin 16): driver supply for ground referenced switches. connect this pin to v cc potential. bg1, bg2 (pins 17, 15): bottom gate driver pins drive the ground referenced n-channel mosfet switches b and c. i ssw1 (pin 18): forward current limit comparator non- inverting input. this pin is normally connected to the source of the n-channel mosfet a (tg1 driven). sw1 (pin 19): ground reference for driver a. gate drive from tg1 will reference to the common point of output switches a and b. tg1, tg2 (pins 20, 12): top gate drive pins drive the top n-channel mosfet switches a and d with a voltage swing equal to v cc C v diode superimposed on the sw1 and sw2 nodes respectively. v bst1 (pin 21): boosted floating driver supply for the buck switch a. this pin will swing from a diode below v cc up to v in + v cc C v diode . i svin (pin 22): forward current limit comparator invert- ing input. this pin is normally connected to the drain of n-channel mosfet a (tg1 driven). v cc (pin 23): internal 4.35v ldo regulator output. the driver and control circuits are powered from this voltage to limit the maximum vgs drive voltage. decouple this pin to power ground with at least a 4.7f ceramic capacitor. for low v in applications, v cc can be bootstrapped from v out through a schottky diode. v in (pin 24): input supply pin for the v cc regulator. a ceramic capacitor of at least 10f is recommended close to the v in and gnd pins. ground (exposed pad pin 25): the gnd and pgnd pins are connected to the exposed pad which must be con- nected to the pcb ground for electrical contact and rated thermal performance.
ltc3785 3785fc b lock diagra m + ? + ? + ? + ? + ? + ? + ? + ? 2.4v tsd 1.225v tg1 bg1 v out low 15mv or 1x i limit g m 1/25k v = 60k/r ilset x10 v = 90k/r ilset uvlo v be 2a i lim(out) i lim(out) 10a max 1a run/ss c ss v sense v out fb rt mode 1.5v ss i lim comp i max comp v c 1.225v run v ref ?6.5% fault logic burst logic i limit set 1/2 limit at v out < 1v gnd/pgnd 1 = burst mode operation 0 = fixed frequency 100% duty charge pump 100% duty charge pump 0 = 15mv 1 = i limit 4.35v reg sampled sampled pgnd 1.8v disable reverse current limit (zero limit for burst) ideal diode bbm sw1 delay v cc v in i limit v in 2.7v to 10v i svin v bst1 v bst2 v out d1 opt d2 opt c out l1 tg1 ma c in c vcc mb md mc c b c a sw1 sw2 sw1 sw2 bg2 v drv pgnd i ssw2 i ssw1 i svout v drv bg1 tg2 adrv i max sw1 pulse sw2 pulse tg2 bg2 v rev bbm sw2 delay bdrv ccm 3785 bd v rev cdrv ddrv reverse limit uv uv + ? +10% osc ov burst ov 1.225v r2 r1 r t r ilset + ? + ? i lset + ? v out c p1 23 22 20 21 19 18 16 17 10 12 11 13 14 15 6 25 5 8 7 2 3 4 1 24
ltc3785 3785fc o pera t ion main control loop the ltc3785 is a buck-boost voltage mode controller that provides an output voltage above, equal to or below the input voltage. the ltc proprietary topology and control architecture also employs drain-to-source sensing (no r sense ) for forward and reverse current limiting. the controller provides all n-channel mosfet output switch drive, facilitating single package multiple power switch technology along with lower r ds(on) . the error amp output voltage (v c ) determines the output duty cycle of the switches. since the v c pin is a fltered signal, it provides rejection of high frequency noise. the fb pin receives the voltage feedback signal, which is compared to the internal reference voltage by the er- ror amplifer. the top mosfet drivers are biased from a foating bootstrap capacitor, which is normally recharged during each off cycle through an external diode when the top mosfet turns off. optional schottky diodes can be connected across synchronous switch b and d to provide a lower drop during the dead time and eliminate effciency loss due to body diode reverse recovery. the main control loop is shut down by pulling the run/ ss pin low. an internal 1a current source charges the run/ss pin and when the pin voltage is higher than 0.7v the ic is enabled. the v c voltage is then clamped to the run/ss voltage minus 0.7v while c ss is slowly charged during start-up. this soft-start clamping prevents inrush current draw from the input power supply. p ower switch control figure 1 shows a simplifed diagram of how the four power switches are connected to the inductor, v in , v out and gnd. figure 2 shows the regions of operation for the ltc3785 as a function of duty cycle d. the power switches are properly controlled so that the transfer between modes is continuous. buck region (v in > v out ) switch d is always on and switch c is always off during buck mode. when the error amp output voltage, v c , is ap- proximately above 0.1v, output a begins to switch. during the off time of switch a, synchronous switch b turns on for the remainder of the switching period. switches a and b will alternate similar to a typical synchronous buck regulator. as the control voltage increases, the duty cycle of switch a increases until the max duty cycle of the converter in buck mode reaches d max_buck , given by: d max_buck = 100 C d4(sw)% where d4(sw) = duty cycle % of the four switch range. d4(sw) = (300ns ? f) ? 100% where f = operating frequency, hz. beyond this point the four switch or buck-boost region is reached. buck-boost or four switch (v in ~ v out ) when the error amp output voltage, v c , is above ap- proximately 0.65v, switch pair ad remain on for duty cycle d max_buck , and the switch pair ac begin to phase in. as switch pair ac phases in, switch pair bd phases out accordingly. when the v c voltage reaches the edge of figure 1. output switch confguration figure 2. operation mode vs v c voltage sw2 bg1 c 3785 f01 sw1 b bg2 l v out v in tg1 d a tg2 boost region buck/boost region four switch pwm 90% d max boost d min boost a on, b off pwm c, d switches buck region d min buck 3785 f02 d max buck d on, c off pwm a, b switches
ltc3785 3785fc opera t ion the buck-boost range, approximately 0.7v, the ac switch pair completely phase out the bd pair, and the boost phase begins at duty cycle, d4(sw). the input voltage, v in , where the four switch region begins is given by: v in = v out 1? 300ns ? f ( ) v the point at which the four switch region ends is given by: v in = v out (1 C d) = v out (1 C 300ns ? f) v boost region (v in < v out ) switch a is always on and switch b is always off during boost mode. when the error amp output voltage, v c , is ap- proximately above 0.7v, switch pair c and d will alternately switch to provide a boosted output voltage. this operation is typical to a synchronous boost regulator. the maximum duty cycle of the converter is limited to 90% typical. burst mode o pera tion during burst mode operation, the ltc3785 delivers energy to the output until it is regulated and then goes into a sleep state where the outputs are off and the ic is consuming only 86a. in burst mode operation, the output ripple has a variable frequency component, which is dependent upon load current. during the period where the converter is delivering en- ergy to the output, the inductor will reach a peak current determined by an on time, t on , and will terminate at zero current for each cycle. the on time is given by: t on = 2.4 v in ? f where f is the oscillator frequency. the peak current is given by: i peak = v in l ? t on i peak = 2.4 f ?l so the peak current is independent of v in and inversely proportional to the f ? l product optimizing the energy transfer for various applications. in burst mode operation the maximum output current is given by: i out(max,burst) 1.2 ? v in f ?l ? v out + v in ( ) a burst mode operation is user-controlled by driving the mode pin high to enable and low to disable. v cc r egulator an internal p-channel low dropout regulator produces 4.35v at the v cc pin from the v in supply pin. v cc powers the drivers and internal circuitry of the ltc3785. the v cc pin regulator can supply a peak current of 100ma and must be bypassed to ground with a minimum of 4.7f placed directly adjacent to the v cc and gnd pins. good bypassing is necessary to supply the high transient cur- rent required by the mosfet gate drivers and to prevent interaction between channels. if desired, the v cc regulator can be connected to v out through a schottky diode to provide higher gate drive in low input voltage applications. the v cc regulator can also be driven with an external 5v source directly (without a schottky diode). t opside mosfet driver s upply (v bst1 , v bst2 ) the external bootstrap capacitors connected to the v bst1 and v bst2 pins supply the gate drive voltage for the top- side mosfet switches a and d. when the top mosfet switch a turns on, the switch node sw1 rises to v in and the v bst2 pin rises to approximately v in + v cc . when the bottom mosfet switch b turns on, the switch node sw1 drops low and the boost capacitor is charged through the diode connected to v cc . when the top mosfet switch d turns on, the switch node sw2 rises to v out and the v bst2 pin rises to approximately v out + v cc . when the bottom mosfet switch c turns on, the switch node sw2 drops low and the boost capacitor is charged through the diode connected to v cc . the boost capacitors need to store about 100 times the gate charge required by the top mosfet
ltc3785 0 3785fc o pera t ion switch a and d. in most applications a 0.1f to 0.47f, x5r or x7r dielectric capacitor is adequate. r un /s oft -s tart (run/ss) the run/ss pin serves as the enable to the ltc3785, soft-start function, and fault programming. a 1a current source charges the external capacitor. once the run/ss voltage is above a diode drop(~0.7v) the ic is enabled. once the ic is enabled, the run/ss voltage minus a diode drop (run/ss C 0.7v) clamps the output of the error amp (v c ) to limit duty cycle. the range of the duty cycle clamping is approximately 0.7v to 1.7v. the run/ss pin is clamped to approximately 2.2v. if current limit is reached the pin will begin to discharge with a current determined by the magnitude of inductor current overcurrent limit, but not to exceed 10a. this function will be described in more detail in the forward current limit section. o scilla tor the frequency of operation is set through a resistor from the rt pin to ground where: f r mhz osc t ? ? ? ? ? ? ? 25000 error amp the error amplifer is a voltage mode amplifer with a reference voltage of 1.225v internally connected to the non-inverting input. the loop compensation components are confgured around the amplifer to provide loop com- pensation for the converter. the run/ss pin will clamp the error amp output, v c , to provide a soft-start function. u ndervoltage and o vervoltage protection the ltc3785 incorporates overvoltage (ov) and undervoltage (uv) functions for fault protection and transient limitation. both comparators are connected to the v sense pin, which usually has a similar voltage divider as the error amplifer without the compensation. the overvoltage threshold is 10% above the reference. the undervoltage threshold is 6.5% below the reference with both comparators having 1.5% hysteresis. during an overvoltage fault, all output switching stops until the fault ceases. during an undervoltage fault, the ic is com- manded to run fxed frequency only (disabled burst mode operation). if the design requires a tightened threshold to one of the comparator thresholds the voltage divider on the v sense pin can be skewed to achieve the threshold. since the range is a constant, tightening the uv threshold will loosen the ov threshold and vice versa. f or ward current limit the ltc3785 is designed to sense the input current by sam- pling the voltage across mosfet a during the on time of the switch (tg1 = high). the sense pins are i svin and i ssw1 . a current sense resistor can be used if increased accuracy is required. the current limit threshold can be programmed with a resistor on the i lset pin. once the desired current limit has been chosen, r ilset can be determined by the following formula: r ilset = 6000 r ds(on)a ?i limit where r ds(on)a = r ds(on) of n-channel mosfet switch a and i limit = current limit in amps. once the voltage between i svin and i ssw1 exceeds the threshold, current will be sourced out of fb to take control of the voltage loop, resulting in a lower output voltage to regulate the input current. this fault condition causes the run/ss capacitor to begin discharging. the level of the discharge current depends on how much the current exceeds the programmed threshold. figure 3 is a simpli- fed diagram of the current sense and fault circuitry. if the current limit fault duration is long enough to discharge the run/ss capacitor below 1.225v, the fault latch is set and will cycle the run/ss capacitor 16 times (1a charging and 1a discharging of the run/ss capacitor) to create an off time of 32 times the soft-start time before the outputs are allowed to switch to restart the output voltage. if the current limit fault level exceeds 150% of the programmed i limit level at any time, the i max comparator is tripped and output switches b and d are turned on to discharge the inductor current for the remainder of the cycle.
ltc3785 3785fc opera t ion to have the power converter latch off on a fault, a pull-up current between 4a and 7a on the run/ss pin will allow the run/ss capacitor to discharge during an extended fault, but will prevent cycling of the fault which will cause the converter to stay off. one method to implement this is by placing a diode (anode tied to v out ) and a resistor from v out to the run/ss pin. the current sourced into run/ss will be v out C 0.7 divided by the resistor value. to ignore all faults source greater than 40a into the run/ss pin (at 1.225v on the run/ss pin). since the maximum fault current is limited, this will prevent any discharging of the run/ss capacitor, the soft-start capacitor will need to be sized accordingly to accommodate the extra charging current at start-up. during an output short-circuit or if v out is less than 1.8v, the current limit folds back to 50% of the programmed level. r everse current limit the ltc3785 can be programmed to provide full class d operation or allowed to source and sink current equal to the current limit set value. this is achieved by asserting a high level on the ccm pin. to minimize the reverse output current, the ccm pin should be driven low or strapped to ground. during this mode only, C15mv typical is allowed across output switch d and is sensed with the i svout and i ssw2 pins. figure 3. block diagram of current limit fault circuitry + ? + ? + ? + ? + ? + ? g m g m = 1/20k i limit comp i max comp turn switches b and d on v = 60k/r ilset (15k/r ilset when v out < 1.8v) x10 v = 90k/r ilset 0.7v 2a 2.2v c ss 1/3 ? i lim(out) 10a max i lim(out) 30a max 1a run/ss v out fb r1 r2 i lim comp i max comp v c c p1 1.225v thermal sd run fault logic i limit set sampled sampled reverse current limit ccm = high = 6k/r ilset ccm = low = 15mv i svin v in v out c out l1 tg1 sw1 sw2 a b d c i ssw2 i ssw1 ccm i svout +? tg2 3785 f03 switch d off 1.225v error amp + ? i lset r ilset bg1 bg2 s s 1 4 3 2 5 15 14 13 12 10 6 17 18 19 20 22
ltc3785 3785fc a pplica t ions i n f or m a t ion inductor selection the high frequency operation of the ltc3785 allows the use of small surface mount inductors. the inductor cur- rent ripple is typically set 20% to 40% of the maximum inductor current. for a given ripple the inductance terms are given as follows: l > v in(min) 2 ? v out ? v in(min) ( ) ? 100 f ?i out(max) ? %ripple ? v out 2 , (boost mode) l > v out ? v in(max) ? v out ( ) ? 100 f ?i out(max) ? %ripple ? v in(max) , (buck mode) where: f = operating frequency, hz %ripple = allowable inductor current ripple, % v in(min) = minimum input voltage (limit to v out /2 minimum for worst-case), v v in(max) = maximum input voltage, v v out = output voltage, v i out(max) = maximum output load current, a for high effciency choose an inductor with a high frequency core material, such as ferrite, to reduce core loses. the inductor should have low esr (equivalent series resistance) to reduce the i 2 r losses, and must be able to handle the peak inductor current without saturating. molded chokes or chip inductors usually do not have enough core to sup- port the peak inductor currents in the 3a to 6a region. to minimize radiated noise, use a toroid, pot core or shielded bobbin inductor. c in and c out selection in boost mode, input current is continuous. in buck mode, input current is discontinuous. in buck mode, the selection of input capacitor, c in , is driven by the need to flter the input square wave current. use a low esr capacitor, sized to handle the maximum rms current. for buck operation, the maximum rms capacitor current is given by: i rms ~i out(max) ? v out v in ? 1? v out v in ? ? ? ? ? ? this formula has a maximum at v in = 2v out , where i rms = i out(max) /2. this simple worst-case condition is commonly used for design because even signifcant deviations do not offer much relief. note that ripple current ratings from ca- pacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. in boost mode, the discontinuous current shifts from the input to the output, so c out must be capable of reducing the output voltage ripple. the effects of esr (equivalent series resistance) and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage. the steady ripple due to charging and discharging the bulk capacitance is given by: v ripple _ boost = i out(max) ? v out ? v in(min) ( ) c out ? v out ? f v ripple _ buck = v out ? v in(max) ? v out ( ) 8 ?l ? c out ? v in(max) ? f 2 where c out = output flter capacitor, f the steady ripple due to the voltage drop across the esr is given by: d v boost,esr = i l(max,boost) ? esr d v buck,esr = v in(max) ? v out ( ) ? v out l ? f ? v in ?esr multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. ceramic capacitors have excellent low esr characteristics but can have a high voltage coeffcient. capacitors are now available with low esr and high ripple current ratings such as os-con and poscap. p ower n-channel mosfet selection and efficiency c onsiderations the ltc3785 requires four external n-channel power mosfets, two for the top switches (switches a and d, shown in figure 1) and two for the bottom switches (switches b and c shown in figure 1). important param-
ltc3785 3785fc applica t ions in f or m a t ion eters for the power mosfets are the breakdown voltage v br(dss) , threshold voltage v gs(th) , on-resistance r ds(on) , reverse transfer capacitance c rss and maximum current i ds(max) . the drive voltage is set by the 4.5v v cc supply. consequently, logic-level threshold mosfets must be used in ltc3785 applications. if the input voltage is expected to drop below 5v, then sub-logic threshold mosfets should be considered. in order to select the power mosfets, the power dissipated by the device must be known. for switch a, the maximum power dissipation happens in boost mode, when it remains on all the time. its maxi- mum power dissipation at maximum output current is given by: pa(boost) = v out v in ?i out(max) ? ? ? ? ? ? 2 ? t ?r ds(on) where t is a normalization factor (unity at 25c) ac- counting for the signifcant variation in on-resistance with t e mperature, typically about 0.4%/c as shown in figure 4. for a maximum junction temperature of 125c, using a value t = 1.5 is reasonable. switch b operates in buck mode as the synchronous rectifer. its power dissipation at maximum output current is given by: pb(buck) = v in ? v out v in ?i out(max) 2 ? t ?r ds(on) switch c operates in boost mode as the control switch. its power dissipation at maximum current is given by: pc(boost) = v out ? v in ( ) ? v out v in 2 ?i out(max) 2 ? t ? r ds(on) + k ? v out 3 ? i out(max) v in ? c rss ? f where c rss is usually specifed by the mosfet manufactur- ers. the constant k, which accounts for the loss caused by reverse recovery current, is inversely proportional to the gate drive current and has an empirical value of 1.0. for switch d, the maximum power dissipation happens in boost mode when its duty cycle is higher than 50%. its maximum power dissipation at maximum output current is given by: pd boost ( ) = v out v in ?i out(max) 2 ? t ?r ds(on) typically, switch a has the highest power dissipation and switch b has the lowest power dissipation unless a short occurs at the output. from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following formula: t j = t a + p ? r th(ja) the r th(ja) to be used in the equation normally includes the r th(jc) for the device plus the thermal resistance from the case to the ambient temperature (r th(ca) ). this value of t j can then be compared to the original, assumed value used in the iterative calculation process. s chot tky diode (d1, d2) selection optional schottky diodes d1 and d2 shown in the block diagram conduct during the dead time between the conduc- tion of the power mosfet switches. they are intended to prevent the body diode of synchronous switches b and d from turning on and storing charge during the dead time. in particular, d2 signifcantly reduces reverse recovery current between switch d turn off and switch c turn on, which improves converter effciency and reduces switch c voltage stress. in order for d2 to be effective, it must be located in very close proximity to swd. figure 4. normalized r ds(on) vs temperature junction temperature (c) ?50 t normalized on-resistance 1.0 1.5 150 3785 f04 0.5 0 0 50 100 2.0
ltc3785 3785fc applica t ions in f or m a t ion closing the feedback loop the ltc3785 incorporates voltage mode control. the control to output gain is given by: g buck = 1.6 ? v in , buck mode g boost = 1.6 ? v out 2 v in , boost mode the output flter exhibits a double-pole response and is given by: f filter _ pole = 1 2 ? ? l ? c out where c out is the output flter capacitor. the output flter zero is given by: f filter _ zero = 1 2 ? ?r esr ? c out where r esr is the capacitor equivalent series resistance. a troublesome feature in boost mode is the right half plane zero (rhp), and is given by: f rhpz = v in 2 2 ? ?i out ?l ? v out the loop gain is typically rolled off before the rhp zero frequency. a simple type i compensation network (figure 5) can be incorporated to stabilize the loop but at a cost of reduced bandwidth and slower transient response. to ensure proper phase margin, the loop must cross over almost a decade before the l-c double pole. the unity gain frequency of the error amplifer with the type i compensation is given by: f ug = 1 2 ? ?r1? c p1 most applications demand an improved transient response to allow a smaller output flter capacitor. to achieve a higher bandwidth, type iii compensation is required as shown in figure 6. two zeros are required to compensate for the double pole response. f pole1 1 2 ? ? 32e3 ? c p1 ?r1 (a very low frequency) f zero1 = 1 2 ? ?r z ? c p1 f zero2 = 1 2 ? ?r1? c z1 f pole2 1 2 ? ?r z ? c p2 figure 5. error amplifer with type i compensation ? + fb error amp 1.225v 3785 f05 r1 r2 v c v out c p1 figure 6. error amplifer with type iii compensation ? + fb error amp 1.225v 3785 f06 r1 c z1 r2 v c r z v out c p1 c p2
ltc3785 3785fc applica t ions in f or m a t ion efficiency c onsiderations the percentage effciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the effciency and which change would produce the most improvement. although all dissipative elements in circuits produce losses, four main sources account for most of the losses in ltc3785 application circuits: 1. dc i 2 r losses. these arise from the resistances of the mosfets, sensing resistor (if used), inductor and pc board traces and cause the effciency to drop at high output currents. 2. t ransition loss. this loss arises from the brief voltage transition time of switch a or switch c. it depends upon the switch voltage, inductor current, driver strength and mosfet capacitance, among other factors. t ransition loss ~ v sw 2 ? i l ? c rss ? f where c rss is the reverse transfer capacitance. 3. c in and c out loss. the input capacitor has the diffcult job of fltering the large rms input current to the regula- tor in buck mode. the output capacitor has the more diffcult job of fltering the large rms output current in boost mode. both c in and c out are required to have low esr to minimize the ac i 2 r loss and suffcient capacitance to prevent the rms current from causing additional upstream losses in fuses or batteries. 4. other losses. optional schottky diodes d1 and d2 are responsible for conduction losses during dead time and light load conduction periods. core loss is the predominant inductor loss at light loads. turning on switch c causes reverse recovery current loss in boost mode. when making adjustments to improve effciency, the input current is the best indicator of changes in effciency. if you make a change and the input current decreases, then the effciency has increased. if there is no change in input current, then there is no change in effciency. 5. v cc regulator loss. in applications where the input voltage is above 5v, such as two li-ion cells, the v cc regulator will dissipate some power due the differential voltage and the average output current to the drive the gates of the output switches. the v cc pin can be driven directly from a high effciency external 5v source if desired to incrementally improve overall effciency at lighter loads. design example as a design example, assume v in = 2.7v to 10v (3.6v nominal li-ion with 9v adapter), v out = 3.3v (5%), i out(max) = 3a and f = 500khz. determine the inductor value setting the inductor ripple to 40% and using the equations in the inductor selection section gives: l > 2.7 ( ) 2 ? 3.3 ? 2.7 ( ) ? 100 500 ? 10 3 ? 3 ? 40 ? 3.3 ( ) 2 = 0.67h l > 3.3 ? 10 ? 3.3 ( ) ? 100 500 ? 10 3 ? 3 ? 40 ? 10 = 3.7h so the worst-case ripple for this application is during buck mode so a standard inductor value of 3.3h is chosen.
ltc3785 3785fc applica t ions in f or m a t ion determine the proper inductor type selection the highest inductor current is during boost mode and is given by: i l(max _ av) = v out ?i out v in ? where = estimated effciency in this mode (use 80%). i l(max _ av) = 3.3 ? 3 2.7 ? 0.8 = 4.6a to limit the maximum effciency loss of the inductor esr to below 5% the equation is: esr l(max) ~ v out ?i out ? %loss i l(max _ av) 2 ? 100 = 24m a suitable inductor for this application could be a coiltron- ics cd1-3r8 which has a rating dc current of 6a and esr of 13m?. choose a proper mosfet switch using the same guidelines for esr of the inductor, one suitable mosfet could be the siliconix si7940dp which is a dual mosfet in a surface mount package with 25m at 2.5v and a total gate charge of 12nc. checking the power dissipation of each switch will ensure reliable operation since the thermal resistance of the package is 60c/w. the maximum power dissipation of switch a and c oc- curs in boost mode. assuming a junction temperature of t j = 100c with 100c = 1.3, the power dissipation at v in = 2.7, and using the equations from the effciency considerations section: pa(boost) = 3.3 2.7 ? 3 ? ? ? ? ? ? 2 ? 1.3 ? 0.025 = 0.43w pc(boost) = 3.3 ? 2.7 ( ) ? 3.3 2.7 2 ? 3 2 ? 1.3 ? 0.025 + 1? 3.3 3 ? 3 2.7 ? 0.45 ? 9 ? 500 ? 10 3 = 0.09w the maximum power dissipation of switch b and d occurs in buck mode and is given by: pb(buck) = 10 ? 3.3 10 ? 3 2 ? 1.3 ? 0.025 = 0.20w pd(boost) = 3.3 10 ? 3 2 ? 1.3 ? 0.025 = 0.10w now to double check the t j of the package with 50c ambient. since this is a dual nmos package we can add switches a + b and c + d worst-case. for applications where the mosfets are in separate packages each devices maximum t j would have to be calculated. t j(pkg1) = t a + ja (pa + pb) = 50 + 60 ? (0.43 + 0.20) = 88c t j(pkg2) = t a + ja (pc + pd) = 50 + 60 ? (0.09 + 0.10) = 60c set the maximum current limit the equation for setting the maximum current limit of the ic is given by: r ilset = 6000 r ds(on)a ?i limit the maximum current is set 25% above i l(peak) to account for worst-case variation at 100c = 6a. r ilset = 6000 0.025 ? 6 = 42k choose the input and output capacitance the input capacitance should flter current ripple which is worst-case in buck mode. since the input current could reach 6a, a capacitor esr of 10m or less will yield an input ripple of 60mv. the output capacitance should flter current ripple which is worst in boost mode, but is usually dictated by the loop response, the maximum load transient and the allowable transient response.
ltc3785 3785fc a pplica t ions i n f or m a t ion pc board l ayout checklist the basic pc board layout requires a dedicated ground plane layer. also, for high current, a multilayer board provides heat sinking for power components. ? the ground plane layer should not have any traces and it should be as close as possible to the layer with power mosfets. ? place c in , switch a, switch b and d1 in one compact area. place c out , switch c, switch d and d2 in one compact area. ? u se immediate vias to connect the components (includ- ing the ltc3785s gnd/pgnd pin) to the ground plane. use several large vias for each power component. ? use planes for v in and v out to maintain good voltage fltering and to keep power losses low. ? f lood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. connect the copper areas to any dc net (v in or gnd). when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3785. ? s egregate the signal and power grounds. all small-signal components should return to the gnd pin at one point. the sources of switch b and switch c should also con- nect to one point at the gnd of the ic. ? place switch b and switch c as close to the controller as possible, keeping the pgnd, bg and sw traces short. ? keep the high dv/dt sw1, sw2, v bst1 , v bst2 , tg1 and tg2 nodes away from sensitive small-signal nodes. ? the path formed by switch a, switch b, d1 and the c in capacitor should have short leads and pc trace lengths. the path formed by switch c, switch d, d2 and the c out capacitor also should have short leads and pc trace lengths. ? the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor. ? connect the v cc decoupling capacitor c vcc closely to the v cc and pgnd pins. ? connect the top driver boost capacitor c a closely to the v bst1 and sw1 pins. connect the top driver boost capacitor c b closely to the v bst2 and sw2 pins. ? connect the input capacitors c in and output capaci- tors c out close to the power mosfets. these capaci- tors carry the mosfet ac current in boost and buck mode. ? connect fb and v sense pin resistive dividers to the (+) terminals of c out and signal ground. if a small v sense decoupling capacitor is used, it should be as close as possible to the ltc3785 gnd pin. ? route i svin and i ssw1 leads together with minimum pc trace spacing. ensure accurate current sensing with kel- vin connections across mosfet a or sense resistor. ? route i svout and i ssw2 leads together with minimum pc trace spacing. ensure accurate current sensing with kelvin connections across mosfet d or sense resistor. ? connect the feedback network close to ic, between the v c and fb pins.
ltc3785 3785fc p ackage descrip t ion uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697) typical a pplica t ion v cc i svin tg1 v sense bg1 fb v c tg2 bg2 sw2 3785 ta02 v bst1 sw1 i ssw1 i svout rt v drv i ssw2 v bst2 ccm i lset mode run/ss v in 1nf 1nf 205k 270pf 1.3k r1 205k 12k r2 121k r t 59k r ilset 42.2k 121k ltc3785 gnd c vcc 4.7f li-ion 2.7v to 4.2v ma = mb = mc = md = 1/2 si7940dy l1 = wrth electronics 744311470 d1 = d2 = pmeg2020ej 9v regulated wall adapter v in 2.7v to 10v v out 3.3v 3a c in 22f ma mb d1 d2 optional optional md mc c a 0.22f c b 0.22f cmdsh-3 cmdsh-3 l1 4.7h c out 100f + 4.00 0.10 (4 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)?to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 2423 1 2 bottom view?exposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uf24) qfn 0105 recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 s 45 chamfer
ltc3785 3785fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number c 3/10 added ltc3785iuf (i-grade) part. refected throughout data sheet 1 through 20 (revision history begins at rev c)
ltc3785 0 3785fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0310 rev c ? printed in usa typical a pplica t ion part number description comments ltc3780 high effciency (up to 98%), synchronous 4-switch buck-boost controller 4v v in 36v, 0.8v v out 30v, ssop-24, 5mm 5mm qfn-32 ltm4605 high effciency buck-boost dc/dc module complete power supply 4.5v v in 20v, 0.8v v out 16v, 15mm 15mm 2.8mm ltm4607 high effciency buck-boost dc/dc module complete power supply 4.5v v in 36v, 0.8v v out 25v, 15mm 15mm 2.8mm ltm4609 high effciency buck-boost dc/dc module complete power supply 4.5v v in 36v, 0.8v v out 34v, 15mm 15mm 2.8mm ltc3533 2a synchronous buck-boost monolithic dc/dc converter 1.8v v in 5.5v, 1.8v v out 5.25v, i q = 40a, i sd < 1a, 3mm 4mm dfn-14 ltc3441 1.2a synchronous buck-boost monolithic dc/dc converter 2.4v v in 5.5v, 2.4v v out 5.25v, i q = 25a, i sd < 1a, 3mm 4mm dfn-12 ltc3440 600ma synchronous buck-boost monolithic dc/dc converter 2.5v v in 5.5v, 2.5v v out 5.5v, i q = 25a, i sd < 1a, 3mm 3mm dfn-10, msop-10 ltc3444 500ma synchronous buck-boost monolithic dc/dc converter 2.7v v in 5.5v, 0.5v v out 5.25v, optimized for wcdma rf amplifer bias, 3mm 3mm dfn-8 ltc3532 500ma synchronous buck-boost monolithic dc/dc converter 2.4v v in 5.5v, 2.4v v out 5.25v, i q = 35a, i sd < 1a, 3mm 3mm dfn-10, msop-10 ltc3531 ltc3531-3 ltc3531-3.3 200ma synchronous buck-boost monolithic dc/dc converter 1.8v v in to 5.5v, 2v v out 5v, i q = 35a, i sd < 1a, 3mm 3mm dfn-8, thinsot-23 module is a registered trademark of linear technology corporation. v cc i svin tg1 v sense bg1 fb v c tg2 bg2 sw2 3785 ta03 v bst1 sw1 i ssw1 i svout rt v drv i ssw2 v bst2 ccm i lset mode run/ss v in 1nf 1nf 205k 270pf 1.3k 205k 12k 59k 66.5k 42.2k 66.5k ltc3785 gnd c vcc 4.7f li-ion 2.7v to 4.2v ma = mb = mc = md = 1/2 si7940dy l1 = rlf7030t-3r3m4r1 d1 = d2 = pmeg2020ej 9v regulated wall adapter v in 2.7v to 10v v out 5v 2a c in 22f ma mb d1 d2 optional optional md mc c a 0.22f c b 0.22f cmdsh-3 cmdsh-3 l1 3.3h c out 100f + li-ion/9v wall adapter to 5v/2a r ela t e d p ar t s

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